Semiconductor device with increased isolation breakdown voltage

ABSTRACT

A semiconductor device includes a semiconductor substrate comprising a P-type lightly doped semiconductor layer; an undoped silicon layer formed on the P-type lightly doped semiconductor layer; a first deep trench isolation and a second deep trench isolation formed from an upper surface of the semiconductor substrate to the undoped silicon layer and filled with insulating films; and a first N-type highly doped buried layer formed on the undoped silicon layer, and disposed between the first deep trench isolation and the second deep trench isolation, wherein the undoped silicon layer surrounds bottoms of the first and second deep trench isolations, and has a thickness greater than a thickness of the first N-type highly doped buried layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119 of KoreanPatent Application No. 10-2022-0043176 filed on Apr. 7, 2022, in theKorean Intellectual Property Office, the entire disclosure of which isincorporated herein by reference for all purposes.

BACKGROUND 1. Field

The following description relates to a semiconductor device forminimizing process changeability and increasing an isolation breakdownvoltage (in short, ISO BV).

2. Description of Related Art

A BCD (Bipolar-CMOS-DMOS) process is essential to configure variousintegrated circuits (ICs) that desire higher power density and operatingfrequency, such as an LED driver, panel bias IC, switching regulator,battery IC, audio, amplifier, and motor driver. The most common powerdevice used in smart power technology (SPT) is a lateral DMOS (LDMOS).The major feature of the LDMOS apparatus is to maintain a high voltageand high current during operation. To expand the applicability of LDMOSdevices, reliability under harsh switching conditions must be improved,a specific on resistance (Rsp) must be minimized, and a breakdownvoltage (BV) must be maximized simultaneously. Meanwhile, LDMOS powerdevices may occupy up to 60% of the chip area, so device designers arefocusing on reducing Ron and minimizing device size to increase thenumber of dies on the wafer.

By combining BCD process technology and deep trench isolation (DTI)technology to manufacture competitive LDMOS of BCD and DTI technology,it is necessary to reduce Rsp, minimize size, and sufficiently increasebreakdown voltage. In particular, the deep trench isolation in the BCDprocess is widely used because it may reduce a chip size. However, whenDTI is applied to BCD technology, there is a limit to increasing theisolation breakdown voltage.

SUMMARY

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription. This Summary is neither intended to identify key featuresor essential features of the claimed subject matter, nor is it intendedto be used as an aid in determining the scope of the claimed subjectmatter.

In a general aspect, a semiconductor device includes a semiconductorsubstrate comprising a P-type lightly doped semiconductor layer; anundoped silicon layer formed on the P-type lightly doped semiconductorlayer; a first deep trench isolation and a second deep trench isolationformed from an upper surface of the semiconductor substrate to theundoped silicon layer and filled with insulating films; and a firstN-type highly doped buried layer formed on the undoped silicon layer,and disposed between the first deep trench isolation and the second deeptrench isolation, wherein the undoped silicon layer surrounds bottoms ofthe first and second deep trench isolations, and has a thickness greaterthan a thickness of the first N-type highly doped buried layer.

A first PN junction may be formed by the P-type lightly dopedsemiconductor layer and the first N-type highly doped buried layer, andthe first PN junction may be formed in the undoped silicon layer.

The first PN junction may be formed closer to the bottoms of the firstand second deep trench isolations than the first N-type highly dopedburied layer.

The semiconductor device may further include a P-type epi-layer formedon the first N-type highly doped buried layer, wherein the undopedsilicon layer is in direct contact with the P-type epi-layer.

The undoped silicon layer may overlap the first N-type highly dopedburied layer.

The semiconductor device may further include a P-type body region and anN-type well region spaced apart from each other and formed on the firstN-type highly doped buried layer; a gate polysilicon layer formed on agate insulating layer, and formed on the P-type body region and theN-type well region; a P-type pickup region and an N-type source regionformed in the P-type body region; and an N-type drain region formed inthe N-type well region.

The semiconductor device may further include a channel stop regionformed under the first and second deep trench isolations and disposed inthe undoped silicon layer.

Each of the first and second deep trench isolations has a side walloxide film—borophosphosilicate glass (BPSG)—air gap structure.

The semiconductor device may further include a third deep trenchisolation and a fourth deep trench isolation formed from the uppersurface of the semiconductor substrate to the undoped silicon layer andfilled with insulating films; and a second N-type highly doped buriedlayer formed on the undoped silicon layer, and disposed between thethird and fourth deep trench isolations, wherein the undoped siliconlayer surrounds bottoms of the third and fourth deep trench isolations,and the undoped silicon layer has a resistance higher than a resistanceof the P-type lightly doped semiconductor layer and has a thicknessgreater than a thickness of the second N-type highly doped buried layer.

A second PN junction may be formed by the P-type lightly dopedsemiconductor layer and the second N-type highly doped buried layer, andthe second PN junction may be formed in the undoped silicon layer.

The second PN junction may be formed closer to the bottoms of the thirdand fourth deep trench isolations than the second N-type highly dopedburied layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a deep trench isolation inaccordance with one or more embodiments of the disclosure.

FIG. 2 illustrates a cross-sectional view of a high voltage deviceformed between deep trench isolations in accordance with one or moreembodiments of the disclosure.

FIG. 3 illustrates a cross-sectional view of a semiconductor device inaccordance with one or more embodiments of the disclosure.

FIG. 4 illustrates a cross-sectional view of a typical semiconductordevice to compare with the semiconductor device of the disclosure.

FIGS. 5 and 6 illustrate simulation results of net doping profiles ofthe semiconductor device of the disclosure and the typical semiconductordevice.

FIGS. 7 and 8 illustrate simulation diagrams illustrating impactionization rate distributions inside the semiconductor device of thedisclosure and the typical semiconductor device.

FIG. 9 illustrates a graph showing electrical characteristics of thesemiconductor device of the disclosure and the typical semiconductordevice.

FIG. 10 illustrates a flow chart of manufacturing process of thesemiconductor device of the disclosure.

Throughout the drawings and the detailed description, the same referencenumerals refer to the same elements. The drawings may not be to scale,and the relative size, proportions, and depiction of elements in thedrawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

The following detailed description is provided to assist the reader ingaining a comprehensive understanding of the methods, apparatuses,and/or systems described herein. However, various changes,modifications, and equivalents of the methods, apparatuses, and/orsystems described herein will be apparent after an understanding of thedisclosure of this application. For example, the sequences of operationsdescribed herein are merely examples, and are not limited to those setforth herein, but may be changed as will be apparent after anunderstanding of the disclosure of this application, with the exceptionof operations necessarily occurring in a certain order. Also,descriptions of features that are known after an understanding of thedisclosure of this application may be omitted for increased clarity andconciseness, noting that omissions of features and their descriptionsare also not intended to be admissions of their general knowledge.

The features described herein may be embodied in different forms, andare not to be construed as being limited to the examples describedherein. Rather, the examples described herein have been provided merelyto illustrate some of the many possible ways of implementing themethods, apparatuses, and/or systems described herein that will beapparent after an understanding of the disclosure of this application.

Throughout the specification, when an element, such as a layer, region,or substrate, is described as being “on,” “connected to,” or “coupledto” another element, it may be “on,” “connected to,” or “coupled to” theother element, or there may be one or more other elements interveningtherebetween. In contrast, when an element is described as being“directly on,” “directly connected to,” or “directly coupled to” anotherelement, there can be no other elements intervening therebetween.

As used herein, the term “and/or” includes any one and any combinationof any two or more of the associated listed items.

Although terms such as “first,” “second,” and “third” may be used hereinto describe various members, components, regions, layers, or sections,these members, components, regions, layers, or sections are not to belimited by these terms. Rather, these terms are only used to distinguishone member, component, region, layer, or section from another member,component, region, layer, or section. Thus, a first member, component,region, layer, or section referred to in examples described herein mayalso be referred to as a second member, component, region, layer, orsection without departing from the teachings of the examples.

Spatially relative terms such as “above,” “upper,” “below,” and “lower”may be used herein for ease of description to describe one element'srelationship to another element as shown in the figures. Such spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. For example, if the device in the figures is turned over,an element described as being “above” or “upper” relative to anotherelement will then be “below” or “lower” relative to the other element.Thus, the term “above” encompasses both the above and below orientationsdepending on the spatial orientation of the device. The device may alsobe oriented in other ways (for example, rotated 90 degrees or at otherorientations), and the spatially relative terms used herein are to beinterpreted accordingly.

The terminology used herein is for describing various examples only, andis not to be used to limit the disclosure. The articles “a,” “an,” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. The terms “comprises,” “includes,”and “has” specify the presence of stated features, numbers, operations,members, elements, and/or combinations thereof, but do not preclude thepresence or addition of one or more other features, numbers, operations,members, elements, and/or combinations thereof.

Due to manufacturing techniques and/or tolerances, variations of theshapes shown in the drawings may occur. Thus, the examples describedherein are not limited to the specific shapes shown in the drawings, butinclude changes in shape that occur during manufacturing.

The features of the examples described herein may be combined in variousways as will be apparent after an understanding of the disclosure ofthis application. Further, although the examples described herein have avariety of configurations, other configurations are possible as will beapparent after an understanding of the disclosure of this application.

A targeted problem of the disclosure is not limited by the problemsmentioned above. A person skilled in the relevant field of technologymay understand other problems from the following description.

A detailed description is given below, with attached drawings.

The one or more examples may solve problems related to the abovetechnical issue, providing a method and isolation structure to obtain anisolation breakdown voltage (ISO BV) higher than an operation voltage ofa semiconductor device for high voltage.

The one or more examples may provide a method to stably maintain anisolation breakdown voltage (ISO BV) despite a process changeability.

The description in this patent discloses new robust deep-trenchisolation (DTI) structures to improve DTI Iso BV and immunity tovariation of Iso BV with process parameters, e.g., silicon loss, channelstop implants, etc.

FIG. 1 illustrates a cross-sectional view of a deep trench isolation inaccordance with one or more embodiments of the disclosure.

A semiconductor substrate 10 may include a shallow trench isolation(STI) 20 and a hard mask pattern 30. The hard mask pattern 30 may beimplemented as an etch stop region when forming a deep trench isolation(DTI) 40. The DTI 40 may have a deeper depth than the STI 20. In anexample, a depth of the DTI 40 may be 19-40 μm, and its width may be1.0-4.0 μm. Its inclination angle may be 88-90°. A channel stop region45 may be formed just under the bottom of the DTI 40 to prevent aleakage current. The DTI 40 may be etched from a top of thesemiconductor substrate 10, and the DTI 40 may be formed with a widththat becomes narrower toward the bottom. The DTI 40 may be filled withseveral insulating films. In an example, the DTI 40 may be filled with aside wall oxide film 50 and gap-fill insulating film 60 with air gap orvoid 70. The side wall oxide film 50 may be deposited by a LPCVD method.The gap-fill insulating film 60 may be implemented byBorophosphosilicate Glass (BPSG) film. The air gap or void 70 may beinside the gap-fill insulating film 60. Another example, a singlematerial without void may be formed inside the DTI 40. Further,inter-layer insulating films 80 and 90 may be formed on the gap-fillinsulating film 60 implemented by BPSG film or Tetraethyl orthosilicate(TEOS) film.

FIG. 2 illustrates a cross-sectional view of a high voltage deviceformed between deep trench isolations in accordance with one or moreembodiments of the disclosure.

In accordance with one or more examples of the disclosure, a highvoltage semiconductor device 100 may include DMOS, LDMOS, EDMOS, and BCDdevices having breakdown voltages over 40V. As illustrated in FIG. 2 ,the high voltage semiconductor device 100 may include P-type lightlydoped semiconductor layer 110; an undoped silicon layer 120 formed onthe P-type lightly doped semiconductor layer 110; a highly doped N-typeburied layer (NBL) 130 formed on the undoped silicon layer 120, whereinthe NBL layer is formed by ion implantation and high-temperature annealprocesses; a P-type epi-layer 140 formed on the highly doped NBL 130;the first and second deep trench isolations 201 and 202 formed acrossthe P-type epi-layer 140 and the undoped silicon layer 120; and a highvoltage device between the first deep trench isolation (DTI) 201 and thesecond deep trench isolation 202. Additionally, the air gap 70 may beformed inside each of the first and the second DTIs 201 and 202. TheP-type channel stop region 45 implemented by implantation may be formedrespectively under the first and the second DTIs 201 and 202. Theimplanted channel stop region 45 may be formed in a portion of theundoped silicon layer 120. A description of the internal structure ofthe first and second DTIs 201 and 202 is the same as the description ofthe structure mentioned in FIG. 1 , and thus will be omitted.

In accordance with one or more examples of the disclosure, the highvoltage semiconductor device 100 may further include a field oxide film210 formed on the P-type epi-layer 140; a N-type drift region or alightly-doped N-type well region (HDNW) 220 and a P-type well region(PW) 230; a P-type body region (PBODY) 240 and a N-type well region (NW)250 formed in the HDNW 220; a gate electrode, i.e. the N-typeheavily-doped polysilicon layer 260; a P-type pickup region 270, aN-type source region 280, and a N-type LDD region 285 formed in thePBODY 240; a N-type drain region 290 formed in the NW 250; and a P-typepickup region 295 formed in the PW 230. Herein, a HDNW means a highvoltage deep N-type well region. NW and PW mean N-type and P-type wellregions, respectively. PBODY means P-type body region.

In FIG. 2 , although the field oxide film 210 is illustrated as a LOCOS,it may be replaced with the STI 20 in FIG. 1 to reduce the size of achip. The gate electrode 260 may have a ring shape. The PBODY 240 andthe source region 280 may be formed inside the ring region, and thedrain region 290 may be formed outside the ring region. As the PBODY 240is surrounded by N-type regions 130, 220, and 250, a fully isolatedstructure may be formed with electrically separated from the P-typelightly doped semiconductor layer 110 or the undoped silicon layer 120.Therefore, a voltage that is different from a ground voltage may beapplied to the source region 280. The same bias voltage may be appliedto the electrodes of the source region 280 and the pickup region 270. Asthe P-type lightly doped semiconductor layer 110 and the undoped siliconlayer 120 are electrically connected to the P-type well region (PW) 230,the ground voltage may be applied.

In accordance with one or more examples of the disclosure, the undopedsilicon layer 120 may be formed on the P-type lightly dopedsemiconductor layer 110 at the beginning of BCD process. A thickness ofthe undoped silicon layer 120 may be a significant process parameter inorder to improve an isolation breakdown voltage. The undoped siliconlayer 120 may be formed starting from the highly doped NBL 130 towardthe P-type lightly doped semiconductor layer 110. The undoped siliconlayer 120 may be formed surrounding bottoms of the first and the secondDTIs 201 and 202. A thickness of the undoped silicon layer 120 may bethicker than that of the highly doped NBL 130. In an example, aresistance of the undoped silicon layer 120 may be greater than that ofthe P-type lightly doped semiconductor layer 110 because the undopedsilicon layer 120 is formed by undoped intrinsic silicon. The undopedsilicon layer 120 is not doped, and it comprises an intrinsic siliconmaterial that does not have N-type or P-type conductivity. The undopedsilicon layer 120 may be a pure semiconductor layer that does not haveN-type or P-type dopant type. Therefore, the number of charge carriersmay be determined by characteristics of material itself, not by anamount of impurities. The undoped silicon layer may be formed by anepitaxial growth. After a manufacturing process is completed, athickness of the undoped silicon layer 120 may become thinner than apredetermined thickness because some of dopants in the highly doped NBL130 may be diffused to the undoped silicon layer 120 during a hightemperature annealing. Therefore, the undoped silicon layer 120 mayoverlap a portion of the NBL. In an example, a thickness of the undopedsilicon layer 120 may range from 20 μm to 25 μm.

In accordance with one or more examples of the disclosure, the highlydoped NBL 130 may be formed by performing an ion implantation processwith antimony (Sb) or phosphorus (P) impurities. After the ionimplantation process, annealing process is performed to activate theimplanted dopants. The highly doped NBL 130 may have a dopingconcentration of 1E17-1E20/cm3 higher than a doping concentration of theundoped silicon region 120 or the P-type lightly doped semiconductorlayer 110, wherein the P-type lightly doped semiconductor layer 110 mayhave a doping concentration of 1E14-1E16/cm3.

In an example, when the nLDMOS, used as a high voltage device, isoperated in a high side (HS) mode, a source voltage may be higher than asubstrate voltage because the source region 280 is connected to a loadof the next stage. To solve the electronic insulation issue, the highlydoped NBL 130 may be disposed under the source region 280. The highlydoped NBL 130 may prevent punch-through between a source region of anN-type LDMOS (nLDMOS) and the P-type lightly doped semiconductor layer110.

The existence of the highly doped NBL 130 may limit the extension of thedepletion region from the P-type lightly doped semiconductor layer 110due to the high doping concentration of the highly doped NBL 130. Inthat case, there may be a limitation to increase a breakdown voltage(BV) in the LDMOS. However, the undoped silicon layer 120 may be helpfulto increase a breakdown voltage (BV) in the LDMOS. A SOI(silicon-on-insulator) layer may be implemented instead of the undopedsilicon layer 120, but the SOI process has disadvantages of high costand low thermal conductivity.

In accordance with one or more examples of the disclosure, the P-typeepi-layer 140 may be formed by an epitaxial growth process. In order toembody a LDMOS device having a breakdown voltage over 100V, a thickP-type epi-layer 140 may be implemented between a highly dopeddrain/N-type source region and the P-type lightly doped semiconductorlayer 110.

FIG. 3 illustrates a cross-sectional view of a semiconductor device fortechnology computer aided design (TCAD) simulation on isolationbreakdown voltage (ISO BV) in accordance with one or more examples ofthe disclosure.

In an embodiment of the disclosure, a semiconductor device 300 includinga first N-type highly doped region (collector) 310 and a second N-typehighly doped region (emitter) 320 is shown as an example for evaluationfor ISO BV and TCAD simulation.

In accordance with one or more examples of the disclosure, thesemiconductor device 300 may include the first to fourth deep trenchisolation 201-204. It may be divided into the first region disposedbetween the first deep trench isolation 201 and the second deep trenchisolation 202; and the second region disposed between the third deeptrench isolation 203 and the fourth deep trench isolation 204. Or, itmay be divided into a high voltage application region between the firstdeep trench isolation 201 and the second deep trench isolation 202; anda low voltage application region between the third deep trench isolation203 and the fourth deep trench isolation 204.

A first highly doped NBL 130 (left) and a second highly doped NBL 130(right) may be disposed respectively in the first region and the secondregion. The first N-type highly doped buried layer 130 (left) is formedon the undoped silicon layer 120, and is disposed between the first deeptrench isolation 201 and the second deep trench isolation 202. Thesecond N-type highly doped buried layer 130 (right) is formed on theundoped silicon layer 120, and is disposed between the third deep trenchisolation 203 and the fourth deep trench isolation 204. The undopedsilicon layer 120 surrounds bottoms of the first to fourth deep trenchisolations 201-204, and has a thickness greater than a thickness of thefirst or second N-type highly doped buried layer 130.

The undoped silicon region 120 and the P-type epi-layer 140 may beformed in direct contact with each other between the second deep trenchisolation 203 and the third deep trench isolation 204.

The semiconductor device 300 may further include the HDNW 220 formed onthe highly doped NBL 130 respectively in the first region or the secondregion, and the NW 250 formed in the HDNW 220. The semiconductor device300 may further include the first N-type highly doped region (collector)310 and the second N-type highly doped region (emitter) 320 formed inthe first region and the second region, respectively. The first N-typehighly doped region (collector) 310 and the second N-type highly dopedregion (emitter) 320 may be formed by a high doping concentration. Thefirst N-type highly doped region (collector) 310 may be electricallyconnected to a collector electrode, and the second N-type highly dopedregion (emitter) 320 may be electrically connected to an emitterelectrode.

A plurality of shallow trench isolations (STI) 20 may be formed atright/left sides of the first N-type highly doped region (collector) 310and the second N-type highly doped region (emitter) 320. The shallowtrench isolation (STI) 20 may be deeper than the first N-type highlydoped region (collector) 310 and the second N-type highly doped region(emitter) 320 but shallower than the NW 250.

An NPN parasitic transistor may comprises the first N-type highly dopedregion (collector) 310, the P-type lightly doped semiconductor layer 110as a base region and the second N-type highly doped region (emitter)320. By applying a high voltage to the first N-type highly doped region(collector) 310, and after applying the ground voltage to the P-typelightly doped semiconductor layer 110 and the second N-type highly dopedregion (emitter) 320, an isolation breakdown voltage (ISO BV) of the NPNparasitic transistor may be measured. That is, the ISO BV may be acollector to emitter breakdown voltage (BVceo or BVces) for the NPNparasitic transistor.

In an embodiment of the disclosure, PN junctions 160 may be formedinside the undoped silicon layer 120. The PN junctions 160 may be formedby a diffusion of dopants of the P-type lightly doped semiconductorlayer 110 and the highly doped NBL 130 toward the undoped silicon layer120 after thermal processes. The PN junctions 160 may be formed closerto bottoms of the first to fourth deep trench isolations 201-204. Thatis, the PN junctions 160 may be formed far from a point 130 a (see FIG.5 ), wherein the point 130 a means a maximum doping concentration of thehighly doped NBL 130. The PN junctions 160 may be formed near bottoms ofthe first to fourth deep trench isolations 201-204.

In an embodiment of the disclosure, based on the PN junctions 160, adepletion region 180 may be formed deeper toward the P-type lightlydoped semiconductor layer 110, rather than the highly doped NBL 130,mainly due to a difference of doping concentrations. That is, a dopingconcentration of the highly doped NBL 130 may be much higher than thatof the P-type lightly doped semiconductor layer 110. Also, by adding theundoped silicon layer 120, a location of the PN junctions 160 may bemoved more toward the P-type lightly doped semiconductor layer 110.Since the undoped silicon layer 120 is an intrinsic silicon layer, itmay support an extension of the depletion region 180. In the drawing,the mark ‘150’ illustrates an edge (boundary line) of the depletionregion below. For reference, based on the PN junctions 160, a depletionregion that is upper than the PN junctions 160 may be generated by theP-type lightly doped semiconductor layer 110. Additionally, a depletionregion that is lower than the PN junctions 160 may be generated by thehighly doped NBL 130.

In an embodiment of the disclosure, the depletion region 180 (dotted)may be largely formed toward the P-type lightly doped semiconductorlayer 110. Since the undoped silicon region 120 has an extremely lowdoping concentration than other regions, the depletion region may beextended to the P-type lightly doped semiconductor layer 110. Therefore,the depletion region may be thick, and accordingly, the isolationbreakdown voltage of the semiconductor device in FIG. 3 may be muchhigher than that of typical semiconductor devices.

FIG. 4 illustrates a cross-sectional view of a typical semiconductordevice to compare with the semiconductor device of the disclosure.

The semiconductor device 400 illustrated in FIG. 4 has no undopedsilicon layer compared to the semiconductor device 300 of FIG. 3 ,although the structure is generally the same. Therefore, the same marksare given in FIG. 4 . That is, in the semiconductor device 400 of FIG. 4, deep trench isolations 201-204 may be formed in the P-type lightlydoped semiconductor layer 110. The device may include the P-type lightlydoped semiconductor layer 110 (base region), the highly doped NBL 130,and the P-type epi-layer 140. The HDNW 220, the NW 250, the first N-typehighly doped region (collector) 310, and the second N-type highly dopedregion (emitter) 320 may be formed in the P-type epi-layer 140. Thefirst N-type highly doped region (collector) 310 and the second N-typehighly doped region (emitter) 320 may be formed with a high dopingconcentration.

In FIG. 4 , the PN junctions 160 may be formed inside the P-type lightlydoped semiconductor layer 110 in the typical semiconductor device 400.The PN junctions 160 may be formed by the diffusion of dopants in thehighly doped NBL 130 and in the P-type lightly doped semiconductor layer110. The PN junctions 160 may be formed closer to the highly doped NBL130. That is, the PN junctions 160 may be formed close to a point 130 a(see FIG. 6 ), where the maximum doping concentration of the highlydoped NBL 130 appears. An area of the depletion region 180 in FIG. 4 issmaller than that of the depletion region 180 in FIG. 3 because of theabsence of an undoped silicon in the typical semiconductor device 400.Accordingly, an ISO breakdown voltage of the typical semiconductordevice 400 may be lower than an ISO breakdown voltage of thesemiconductor device 300 of the disclosure. In the drawing, the mark‘150’ illustrates an edge (boundary line) of the depletion region below.

FIGS. 5 and 6 illustrate simulation results of net doping profiles ofthe semiconductor device of one or more examples and the typicalsemiconductor device, respectively.

FIG. 5 illustrates the semiconductor device 300 of one or more exampleswith the undoped silicon layer, and FIG. 6 illustrates the typicalsemiconductor device 400 without the undoped silicon layer.

In FIG. 5 , the undoped silicon layer 120 may be formed on the top ofthe P-type lightly doped semiconductor layer 110. Its typical initialthickness is 20 μm. The P-type epi-layer 140 may be formed on theundoped silicon layer 120. Its typical thickness is 10 μm.

The highly doped buried layer 130 may be disposed at the boundary of theundoped silicon layer 120 and the P-type epi-layer 140. When forming thehighly doped NBL 130, dopants may be implanted toward the undopedsilicon layer 120. Therefore, the highly doped NBL 130 may be partiallyoverlapped with the undoped silicon layer 120. Accordingly, the finalthickness of the undoped silicon layer 120 may be reduced than theinitial thickness 20 μm. In an example, it may be below 15 μm.

As shown in FIG. 5 , the P-type lightly doped semiconductor layer 110may have the doping concentration of 1E14-1E16/cm³, and the highly dopedNBL 130 may have the doping concentration of 1E17-1E20/cm³. The dopingconcentration of the highly doped NBL 130 may be higher than the dopingconcentration the P-type lightly doped semiconductor layer 110, about 3to 4 order. Therefore, based on the PN junctions 160, the depletionregion 180 may be largely formed toward the P-type lightly dopedsemiconductor layer 110, rather than the highly doped NBL 130. A firstPN junction 160 (left) may be formed closer to the bottoms of the firstand the second deep trench isolations 201 and 202, rather than the point130 a where the maximum doping concentration of the highly doped NBL 130appears.

The PN junctions 160 may be located inside the undoped silicon layer120. The PN junctions 160 may be formed by diffusion of the dopants inthe P-type lightly doped semiconductor layer 110 and the highly dopedNBL 130 into the undoped silicon layer 120 after thermal processes. Adoping concentration near the PN junctions 160 may be 1E11-1E13/cm³.Since the PN junctions 160 is formed in the undoped silicon layer 120,the doping concentration near the PN junctions 160 is supposed to below. Therefore, the depletion region 180 may be much larger than that oftypical devices without the undoped silicon layer. The maximum width ofthe depletion region 180 may be about 14 μm from the top of thedepletion region to the bottom of the depletion region. An ISO BV may beover 150V (see FIG. 9 ). It is because the undoped silicon layer 120,which is an intrinsic semiconductor region, may be disposed between theP-type lightly doped semiconductor layer 110 and the highly doped NBL130. The undoped silicon layer 120 is an intrinsic semiconductor regionand work as a buffer layer.

In FIG. 6 , the maximum width of the depletion region 180 may be about 8μm. Compared with FIG. 5 , an area of the depletion region 180 in FIG. 6may be relatively small. An ISO BV of the device in FIG. 6 may be120-130V (see FIG. 9 ). In FIG. 6 , a doping concentration near the PNjunctions 160 may be 1E16-1E17/cm³. Compared with FIG. 5 , the dopingconcentration near the PN junctions 160 in FIG. 6 may be higher over 3-4order. A first PN junction 160 (left) may be formed closer to the point130 a where the maximum doping concentration of the highly doped NBL 130appears, rather than near the bottoms of the first and the second deeptrench isolations 201 and 202. Since the doping concentration near thePN junctions 160 in FIG. 6 is higher than the disclosure, the ISO BV ofthe device in FIG. 6 cannot be higher than that in FIG. 5 .

FIGS. 7 and 8 illustrate simulation diagrams illustrating impactionization rate distributions inside the semiconductor device of thedisclosure and the typical semiconductor device.

In the drawings, the red portion represents a high impact ionizationrate, while the blue portion represents a low impact ionization rate. Ahigh impact ionization rate may refer to that an electric field islocally high after applying a high reverse bias voltage to a firstN-type highly doped region (collector) 310. Acceleration may be possibleby obtaining an energy of electrons or holes from the high electricfield, and a new electron-hole pair generation rate may increase aftercolliding atoms in a semiconductor grid, resulting in increasingcurrent.

Comparing FIG. 7 with FIG. 8 , the example of FIG. 7 shows lower impactionization rate and more uniformly distributed electric field contoursin the depletion region of the PN junction 160 between the DTIs 201 and202. Also, due to the more uniformly distributed electric field contoursin the depletion region, an ISO BV of the structure in FIG. 7 mayincrease more. On the other hand, in the typical structure in FIG. 8 ,the impact ionization rate is locally high near the PN junction adjacentto DTI in the depletion region. Additionally, due to a high andintensive electric field throughout the narrow area, there is alimitation to increase an ISO BV accordingly. The disclosure may suggesta new semiconductor device structure including the undoped silicon layer120 to minimize a dependency of process changeability and to increase aDTI breakdown voltage or ISO BV. By the undoped silicon layer 120 in thenew device, a PN junction depletion region may be become larger and isformed between the P-type lightly doped semiconductor layer 110 and thehighly doped N-type buried layer 130, and the contours of the electricfield or the impact ionization rate contours may not be concentratedlocally. When having the undoped silicon layer 120 as suggested in thedisclosure, it may be beneficial to minimize a dependency of processchangeability and to increase a DTI breakdown voltage or ISO BV.

FIG. 9 illustrates a graph illustrating electrical characteristics ofthe semiconductor device of the disclosure and the typical semiconductordevice.

FIG. 9 shows ISO BV values according to simulation results of astructure of the disclosure having the undoped silicon layer and thetypical structure without the undoped silicon layer. In FIG. 3 or FIG. 4, a high voltage may be applied to the first N-type highly doped region(collector) 310, and the ground voltage may be applied to the secondN-type highly doped region (emitter) 320 and the P-type lightly dopedsemiconductor layer (base) 110. Then, an isolation breakdown voltage(ISO BV) may be measured. That is, the ISO BV may be an emitter tocollector breakdown voltage of NPN parasitic BJT. The simulation isconducted in 0.18 μm BCD process, based on 80V DMOS, and it isdiscovered that the typical semiconductor device 400 has the ISO BV of110-130V. On the other hand, the semiconductor device 300 of thedisclosure has the ISO BV over 150V, which represents that the ISO BVincreases. As described earlier, it is because the electric field andimpact ionization rate contours may have more even distribution due tothe undoped silicon layer 120.

Accordingly, the disclosure may manufacture a semiconductor device withISO BV higher than that of a typical case, by adding the undoped siliconlayer (undoped Si) 120 formed by the intrinsic silicon that is undopedand formed between the P-type lightly doped semiconductor layer 110 andthe P-type epi-layer 140. The highly doped N-type buried layer 130 maybe formed on the undoped silicon layer 120 (undoped Si) by diffusion ofimpurities in a thermal process, after applying ion implantation.

Meanwhile, in one or more examples of the disclosure, the ISO BV may bemore improved by adjusting a thickness of the undoped silicon layer 120with a DTI depth of 25 μm. In an example, when a thickness of theundoped silicon layer 120 is 5-15 μm in the simulation, the ISO BV isabout 120-140V, which is approximately 5.6% higher than the typical caseof 110-130V without the undoped silicon layer. When the thickness of theundoped silicon layer 120 is 10-30 μm, the ISO BV may be improved higherthan 150V. There is no significant change in ISO BV when the thicknessof the undoped silicon layer 120 becomes much thicker over a certainpoint. Based on the results, the thickness of the undoped silicon layer120 in the disclosure may be desired to be 10-30 μm, but it is notlimited thereto.

FIG. 10 illustrates a flow chart of manufacturing process of thesemiconductor device of the disclosure.

In operation 110, the undoped silicon layer 120 may be formed on theP-type lightly doped semiconductor layer 110. A thickness of the undopedsilicon layer 120 may be 10-30 μm.

In operation 120, the highly doped NBL 130 may be formed on the undopedsilicon layer 120. When forming the highly doped N-type buried layer130, an area of the highly doped NBL 130 may be extended toward theundoped silicon layer 120. Therefore, the thickness of the undopedsilicon layer 120 may be practically reduced than the initial thickness.That is, it may be reduced as much as an extended thickness of thehighly doped NBL 130 into the undoped silicon layer 120.

In operation 130, the P-type epi-layer 140 (doped semiconductor layer)may be formed on a top of the highly doped NBL 130, having a thicknessof 5-15 μm. The P-type epi-layer 140 (uniformly doped semiconductorlayer) may be formed by an epitaxial growth.

In operation 140, a high voltage device may be formed in the P-typeepi-layer 140. To form the high voltage device, the HDNW 220 may beformed, and the NW 250 may be formed in the HDNW 220. The first N-typehighly doped region (collector) 310 and second N-type highly dopedregion (emitter) 320 may be formed in order in the NW 250.

In operation 150, after forming the high voltage device, the first tofourth DTI 201-204 may be formed in the semiconductor substrate 10. Or,the first to fourth DTI 201-204 may be formed before forming the highvoltage device. The first to fourth DTI 201-204 may be started from thesurface of the P-type epi-layer 140, and they may penetrate the HDNW 220and the highly doped NBL 130 into the undoped silicon layer 120. A deeptrench may be formed through an etching process. After forming the deeptrench, a channel stop region 45 may be formed through an ionimplantation inside the trench. An insulating film, for examples, BPSG,oxide film, or undoped polysilicon may fill the deep trenches. A void orair gap may be formed inside the deep trench.

In operation 160, contact plugs may be formed to contact the sourceregion, the drain region and pick-up region.

According to one or more examples, by adding an undoped silicon layeronly between a P-type lightly doped layer of a semiconductor devicehaving dual deep trench isolations and an N-type highly doped buriedlayer, it may increase and stabilize the isolation breakdown voltage(ISO BV) by expanding a silicon depletion region between DTIs andpreventing local intensification of electric field and impact ionizationrate contours in the depletion region.

According to one or more examples, by adding an undoped silicon layer, adepletion region may be formed larger than a typical structure, anddistributions of electric field and impact ionization rate contours maybecome more uniform and less intensified.

While this disclosure includes specific examples, it will be apparentafter an understanding of the one or more examples of this applicationthat various changes in form and details may be made in these exampleswithout departing from the spirit and scope of the claims and theirequivalents. The examples described herein are to be considered in adescriptive sense only, and not for purposes of limitation. Descriptionsof features or aspects in each example are to be considered as beingapplicable to similar features or aspects in other examples. Suitableresults may be achieved if the described techniques are performed in adifferent order, and/or if components in a described system,architecture, device, or circuit are combined in a different manner,and/or replaced or supplemented by other components or theirequivalents. Therefore, the scope of the disclosure is defined not bythe detailed description, but by the claims and their equivalents, andall variations within the scope of the claims and their equivalents areto be construed as being included in the disclosure.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate comprising a P-type lightly doped semiconductorlayer; an undoped silicon layer formed on the P-type lightly dopedsemiconductor layer; a first deep trench isolation and a second deeptrench isolation formed from an upper surface of the semiconductorsubstrate to the undoped silicon layer and filled with insulating films;and a first N-type highly doped buried layer formed on the undopedsilicon layer, and disposed between the first deep trench isolation andthe second deep trench isolation, wherein the undoped silicon layersurrounds bottoms of the first and second deep trench isolations, andhas a thickness greater than a thickness of the first N-type highlydoped buried layer.
 2. The semiconductor device of claim 1, wherein afirst PN junction is formed by the P-type lightly doped semiconductorlayer and the first N-type highly doped buried layer, and the first PNjunction is formed in the undoped silicon layer.
 3. The semiconductordevice of claim 2, wherein the first PN junction is formed closer to thebottoms of the first and second deep trench isolations than the firstN-type highly doped buried layer.
 4. The semiconductor device of claim1, further comprising: a P-type epi-layer formed on the first N-typehighly doped buried layer, wherein the undoped silicon layer is indirect contact with the P-type epi-layer.
 5. The semiconductor device ofclaim 1, wherein the undoped silicon layer overlaps the first N-typehighly doped buried layer.
 6. The semiconductor device of claim 1,further comprising: a P-type body region and an N-type well regionspaced apart from each other and formed on the first N-type highly dopedburied layer; a gate polysilicon layer formed on a gate insulatinglayer, and formed on the P-type body region and the N-type well region;a P-type pickup region and an N-type source region formed in the P-typebody region; and an N-type drain region formed in the N-type wellregion.
 7. The semiconductor device of claim 1, further comprising: achannel stop region formed under the first and second deep trenchisolations and disposed in the undoped silicon layer.
 8. Thesemiconductor device of claim 1, wherein each of the first and seconddeep trench isolations comprises a side wall oxide film,borophosphosilicate glass (BPSG) film, and an air gap.
 9. Thesemiconductor device of claim 1, further comprising: a third deep trenchisolation and a fourth deep trench isolation formed from the uppersurface of the semiconductor substrate to the undoped silicon layer andfilled with insulating films; and a second N-type highly doped buriedlayer formed on the undoped silicon layer, and disposed between thethird and fourth deep trench isolations, wherein the undoped siliconlayer surrounds bottoms of the third and fourth deep trench isolations,and the undoped silicon layer has a resistance higher than a resistanceof the P-type lightly doped semiconductor layer and has a thicknessgreater than a thickness of the second N-type highly doped buried layer.10. The semiconductor device of claim 9, wherein a second PN junction isformed by the P-type lightly doped semiconductor layer and the secondN-type highly doped buried layer, and the second PN junction is formedin the undoped silicon layer.
 11. The semiconductor device of claim 10,wherein the second PN junction is formed closer to the bottoms of thethird and fourth deep trench isolations than the second N-type highlydoped buried layer.
 12. A semiconductor device, comprising: a P-typelightly doped semiconductor layer; an undoped silicon layer formed onthe P-type lightly doped semiconductor layer; a highly doped N-typeburied layer (NBL) formed on the undoped silicon layer; a P-typeepi-layer formed on the highly doped NBL; a first deep trench isolation(DTI) and a second DTI formed across the P-type epi-layer and theundoped silicon layer; and a high voltage semiconductor device formedbetween the first DTI and the second DTI, wherein the undoped siliconlayer surrounds bottoms of the first and second DTIs, and has athickness greater than a thickness of the highly doped NBL.
 13. Thesemiconductor device of claim 12, further comprising a P-type channelstop region formed respectively under the first and the second DTIs,wherein the P-type channel stop region is formed in a portion of theundoped silicon layer.
 14. The semiconductor device of claim 12, whereina PN junction is formed by the P-type lightly doped semiconductor layerand the highly doped NBL, and the PN junction is formed in the undopedsilicon layer.
 15. The semiconductor device of claim 14, wherein the PNjunction is formed closer to bottoms of the first and second DTIs thanthe highly doped NBL.